How to access DDR memory from the host

Question

Hi,  
  
I am looking for information explaining how to access DDR memory from host, but NOT from logic contained in the CL.  
Here is the background:  
Using 2 FPGA instance, I was able to do send data from 1st FPGA pciemaster to the 2nd FGPA ddr.  
Now I want to read the 2nd FPGA DDR data and do data compare, not hardware compare as implemented in cl_tst module.  
  
Please advice on to achieve this.  
  
Regards,  
Venkat

Answer

Hello,  
  
I am assuming your design uses PCIS interface from Shell to provide datapath to the Host Memory. Our example CL_DRAM_DMA has this datapath where PCIS interface feeds an interconnect which then connects to all four DDR. Host can access the PCIS interface (and hence the DDR) through PF0 BAR4 address exposed to the Host as shown below:  
https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Fpga_Pcie_Memory_Map.md#memory-map-per-slot  
  
AWS provides peek/poke APIs to access the PF/BARs from the host. You should be able to access PF0-BAR4 using APIs below:  
https://github.com/aws/aws-fpga/blob/master/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c#L337  
https://github.com/aws/aws-fpga/blob/master/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c#L385  
  
Please let us know if you run into any issues or have any questions.  
  
Thanks!  
Chakra

Answer

Hi Chakra,  
  
I was able to access either FPGA's BAR4.  
Thanks for pointing to the API's and doc.  
  
Regards,  
Venkat

How to access DDR memory from the host

相关内容