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Hello,
The FPGAs in F1 systems have DDR-2133, 72-bits (ECC) DIMMs. Since ECC is enabled, only 64 bits of bus is used for data transfers.
So theoretical max bandwidth will be = 2133 MT/s * 8 Bytes = ~17 GBytes/s
The DDR-Controller wrapped inside sh_ddr.sv (https://github.com/aws/aws-fpga/blob/master/hdk/common/shell_v04261818/design/sh_ddr/synth/sh_ddr.sv) is a Xilinx IP which provides 512-bit AXI4 interface for the user logic. This IP can be run at a max speed of 250MHz. Hence user logic should be able to run at 250MHz * 64 Bytes (512bits) = ~16 GBytes/s
The DDR Controller abstracts lower level DDR details for the user logic. As such, any AXI4 write transactions presented to the AXI4 interface of the controller will be presented to the DDR memory. Similarly AXI4 read requests will be responded with data from the DDR memory. sh_ddr.sv supports upto 32 outstanding transactions on Reads.
Please let us know if you need any additional details.
Thanks!
Chakra
Thank you for the info, Chakra. The content in the tutorial video was incorrect - it mentioned 16 Gbit/sec whereas your calculations of 16GByte/sec make sense. One additional question I had is about the latency of the DDR read/write access in 250 MHz clocks. For instance, according to your reply, the custom logic could issue back-to-back 512-bit reads to the DDR via AXI4 over 32-cycles. Are there any specs on how long on average it would take in clocks for the reads to return data?
Azimuth
Hi Azimuth,
Currently we don't benchmark the average latency for DDR AXI buses. The reason is that there could be many variables involved in that, for example, DDR traffic pattern, burst size, etc, which depend on the customer design and we don't have control over them. Instead, we provide a good example design (https://github.com/aws/aws-fpga/tree/master/hdk/cl/examples/cl_dram_dma) that you can leverage to measure the average latency with specific traffic patterns that you think are better fit for the design. I hope this helps.
Thanks,
- Chen
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