Hi,
the Shell specification says:
This interface uses single clock pulses for the req/ack. The CL asserts (active high) cl_sh_apppf_irq_req[x] for a single clock to assert the interrupt request to the SH. The SH will respond with a single clock pulse on sh_cl_apppf_irq_ack[x] to acknowledge the interrupt.
As I understand it, the Shell uses the Xilinx PCIe DMA core (XDMA) for DMA and user interrupts. Xilinx PG195 says about the user interrupts:
After a usr_irq_req bit is asserted, it must remain asserted until the corresponding usr_irq_ack bit is asserted. The usr_irq_ack bit assertion indicates the requested interrupt has been sent on PCIe. For MSI-X, once this ack has been observed, the usr_irq_req bit can be deasserted.
Does the shell have additional logic to handle this requirement? I.e. does my CL need to send a single clock pulse as stated in the shell specification or must the CL assert the request line until it got ack'ed?
