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Hi aiquanta,
Xilinx publish detailed information on primitives supported by a specific device architecture in its architecture libraries guide. Here is an example: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug974-vivado-ultrascale-libraries.pdf. Most time, you should be able to find answers from this document. Xilinx forum will be another good source for finding this type of information. Regarding to the warning [Synth 8-5856], I think you're right. By switching to 128, it's very likely that it breaks some implicit rules set for the maximum BRAM cascading number or something similar.
In addition, I would strongly recommend you to follow the Xilinx's guidance on the coding style for primitive inference (Here is a reference, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug974-vivado-ultrascale-libraries.pdf). There is a small chance sometimes the synthesizer might not be able to interpret the code correctly. It would be good to avoid that as much as possible. Hope this helps you.
Thanks,
- Chen
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