Questions tagged with FPGA Development
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Hi,
we are seeing performance drop when we access specific address pattern from DDR. Please find the below details.
in a single test we read same address repeatedly as mentioned below
rd_addr is...
1
answers
0
votes
259
views
asked 9 months agolg...
Hi there,
Is there a way that CL can control the XDMA inside the Shell in the AWS F1? I have a usecase where CL needs to setup a DMA transfer from internal memory to Host.
A separate question, Is...
1
answers
0
votes
205
views
asked 9 months agolg...
XRT ERROR : failed to load xclbin : input output error hello_world tutorial on AWS F1 / AMI 1.12.2lg...
I encountered an error during the official tutorial. (https://github.com/aws/aws-fpga/blob/master/Vitis/README.md)
I followed the tutorial in
AWS F1(f1.2xlarge) instance / oregon
FPGA Developer AMI...
Accepted AnswerFPGA Development
3
answers
0
votes
316
views
asked 10 months agolg...
I needed a phase-shifted (relative to the clk_main_a0) clock for my CL, and I implemented that using an MMCME4_ADV in my design. I ran into the well-known sub-optimal placement issues. When I did this...
1
answers
0
votes
204
views
asked 10 months agolg...
Hi,
I have to connect my design with ARM processor and I have to create 2 AFIs with the same design. One is transmitter and another is receiver. But both have to be configured in a different way so...
Accepted AnswerFPGA Development
1
answers
0
votes
246
views
asked 10 months agolg...
Hi,
Getting the following error while implementing my custom logic.
ERROR: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net...
Accepted AnswerFPGA Development
3
answers
0
votes
371
views
asked a year agolg...
I am trying to do some optimization for network traffic handling by utilizing FGPA acceleration on AWS [F1?].
Per my understanding the F1 service is based on Xilinx Alveo SmartNIC hardware.
So my...
2
answers
1
votes
291
views
asked a year agolg...
Hi,
I want to read the signal ** irq_req[15:0]** from the shell.
How to read it..?
Kindly help me.
Thank you
Accepted AnswerFPGA Development
1
answers
0
votes
249
views
asked a year agolg...
Hello,
I'm trying to elaborate with the small shell. First of all, no AMI from AWS with Vivado 2020.2 is available. Probably I can use Vivado 2021.2 to generate IPs, but according to the...
1
answers
0
votes
218
views
asked a year agolg...
Can multiple DCPs be loaded into an AFI and only enable certain DCPs at a time on the fly?
2
answers
0
votes
247
views
asked a year agolg...
Can I have an estimated load time when loading an already generated AFI into a FPGA slot on an F1 instance?
I see that the load time can be decreased through caching and data retention. I have read...
1
answers
0
votes
301
views
asked a year agolg...
Hello,
I am implementing an FPGA IP connected to the AWS shell through AXI interface. The IP performs :
loading data from DDRA,
calculation on these data
storing the result in DDRB
The IP...
1
answers
0
votes
200
views
asked a year agolg...