Questions tagged with FPGA Development
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DMA registerslg...
Hello,
I was unable to locate the documentation for configuration registers in the shell which XDMA driver uses to control DMA operation.
Can you please provide the pointer?
Thanks
4
answers
0
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253
views
asked 3 years agolg...
Working my way through the walkthrough on this page:
- https://github.com/aws/aws-fpga/blob/master/Vitis/README.md
Upon performing these steps:
$ cd...
3
answers
0
votes
1114
views
asked 3 years agolg...
I was trying to follow steps here:
https://github.com/aws/aws-fpga/blob/master/Vitis/docs/Setup_AWS_CLI_and_S3_Bucket.md
But this suggested step failed for me:
$ aws s3 mb...
1
answers
0
votes
340
views
asked 3 years agolg...
Hi,
I am using AWS F1 for FPGA development from an year I had this basic question from long time. Right now I have selcted a0 clock recipe for my design which is main clock. As per my...
5
answers
0
votes
396
views
asked 3 years agolg...
DDR bandwidthlg...
I'd like to calculate the peak bandwidth available to custom logic using the AWS F1 DDR interface. Tutorial video 2 has the following statements about DDR:
* 4 DDR channels each having 16Gb,...
3
answers
0
votes
474
views
asked 3 years agolg...
Combinatorial Looplg...
Hello,
I am using Vitis flow to create an RTL kernel.
I have an intentional 'combinatorial loop':
In the design, multiplexers are used to connect some number of LUTS in different ways...
3
answers
0
votes
216
views
asked 3 years agolg...
3D RAM as registerlg...
I am creating a 3 D signal as shown below and I understand that this would be implemented as register.
**"logic \\[N-1:0\]\\[N-1:0\]\\[1:0\] X;"**
But When I run synthesis with N=64 it works...
1
answers
0
votes
443
views
asked 3 years agolg...
Hi,
How can we add a wire (or some wires) to connect an HLS kernel and an RTL kernel in Vitis?
I want to use the RTL kernel to read some values in the HLS kernel for debugging. Can we avoid...
1
answers
0
votes
399
views
asked 3 years agolg...
Hi. This is a follow-up to post https://forums.aws.amazon.com/thread.jspa?messageID=990108󱮜.
I successfully installed NICE DCV for FPGA development using the guide...
3
answers
0
votes
318
views
asked 3 years agolg...
Hi. This is a follow-up question to: https://forums.aws.amazon.com/message.jspa?messageID=990108#990108
I am using Vitis HLS GUI on AWS M5.xlarge instance with FPGA Developer AMI 1.10.0
I am...
2
answers
0
votes
302
views
asked 3 years agolg...
Hi.
I was trying to launch Vitis HLS GUI with FPGA Deveoper AMI 1.10.0.
I did "git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR",
and then "cd $AWS_FPGA_REPO_DIR" and then...
6
answers
0
votes
766
views
asked 3 years agolg...
Hi,
I am looking for information explaining how to access DDR memory from host, but NOT from logic contained in the CL.
Here is the background:
Using 2 FPGA instance, I was able to do send...
2
answers
0
votes
281
views
asked 3 years agolg...