Questions tagged with FPGA Development
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Hey guys,
I was wondering about the provenance of these three constraints that appear in some but not all of the example designs. Under what circumstances are they required? In my designs, now...
3
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206
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asked 3 years agolg...
Hi there,
I was having a play with the AMI just now, and I was thinking to see if I could build something for the older Artix 7 series parts (xc7a100tcsg324-3).
But I'm getting the...
1
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0
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251
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asked 3 years agolg...
I am following the HDK getting started guide, in particular I am trying to execute the "...
2
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0
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326
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asked 3 years agolg...
Hi,
I have a design which split into two modules and I need to load each module into seperage FPGAs. (in this case 2 FPGA's).
Without AWS, I would have used two FPGA boards each loaded with a...
6
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0
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336
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asked 3 years agolg...
Hi,
I am new to AWS FPGA Development.
My task is, Using f1.x4large instance, I need to transfer packetized data from one FPGA to another FPGA.
After power-on, by design one FPGA is defined as...
4
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0
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270
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asked 3 years agolg...
Hi,
I am new to AWS FPGA Development.
My task is, Using f1.x4large instance, I need to transfer packetized data from one FPGA to another FPGA.
After power-on, by design one FPGA is defined as...
1
answers
0
votes
251
views
asked 3 years agolg...
I'm using 1.4.8 still while we're working to upgrade in https://forums.aws.amazon.com/thread.jspa?threadID=338653.
My understanding is that URAMs are not initialized to 0 when the AGFI is loaded...
3
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0
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196
views
asked 3 years agolg...
Hello all,
I've built a design where I planned to test XDMA functionality, as well as Peek/Poke functionality.
Here is the image of the design:
https://imgur.com/Mx4HVDq
Address map: ...
4
answers
0
votes
311
views
asked 3 years agolg...
Hey guys,
I want to add DDR to my FPGA project and as a first step I'm trying to run the CL_DRAM_DMA "test_dram_dma_hwsw_cosim" simulation example with C++ instead of C compiler.
First I had...
1
answers
0
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221
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asked 3 years agolg...
Hi
I am getting an error when I try create an AFI with a 2020.2 Vitis .xclbin.
I'm using aws-fpga v1.4.19.
It seems like Vivado 2020.1 is being used.
...
1
answers
0
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312
views
asked 3 years agolg...
Hi everyone!
I am trying to build XRT for Xilinx SDX 2018.2 and using Xilinx community AMI or AWS FPGA AMI v1.5.1. I am having problem with installing devtoolset 6. I have tried some workarounds...
1
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0
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216
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asked 3 years agolg...
DMA questionslg...
I’m working on optimizing my project, which uses DMA, and have a few questions about best practices on the software side of things as I’m more of an RTL person.
My design is a search engine that...
2
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0
votes
269
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asked 3 years agolg...